EDA三八译码器程序.docVIP

library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity clk_div is port(clk:in std_logic; clk_div:out std_logic); end clk_div; architecture rt1 of clk_div is signal q_temp:integer range 0 to 5999999; begin process(clk) begin if(clkevent and clk=1) then if(q_temp=5999999) then q_temp=0; else q_temp=q_temp+1; end if; end if; end process; process(clk) begin if(clkevent and clk=1) then if(q_temp=5999999) then clk_div=1; else clk_div=0; end if; end if; end process; end rt1; library ieee; use ieee.std_logic_1164.all; entity seg7 is port(q: in std_logic_vector(3 downto 0); segment: out std_logic_vector(0 to 7)); end seg7; architecture rt1 of seg7 is begin process(q) begin case q is when 0000= segment when 0001= segment when 0010= segment when 0011= segment when 0100= segment when 0101= segment when 0110= segment when 0111= segment when 1000= segment when 1001= segment when others= segment =XXXXXXXX; end case; end process; end rt1; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity count3081 is port( enable:in std_logic; clk0:in std_logic; q1:out std_logic_vector(3 downto 0); q2:out std_logic_vector(3 downto 0); q3:out std_logic_vector(3 downto 0); q4:out std_logic_vector(3 downto 0)); end count3081; architecture rt1 of count3081 is signal q1_temp,q2_temp,q3_temp,q4_temp:std_logic_vector(3 downto 0); begin process(clk0) begin if(clk0event and clk0=1)then if(enable=1)then if(q4_temp=0011 and q3_te