全数字硬件化锁相环参数分析与设计-电工技术学报.pdfVIP

20 15 年 1 月 电 工 技 术 学 报 Vol.30 No. 2 第 30 卷第 2 期 TRAN SACTION S OF CHINA ELECTROTECHNICAL SOCIETY Jan . 20 15 全数字硬件化锁相环参数分析与设计 刘亚静,范瑜 北京交通大学电气工程学院 北京 100044 摘要 基于FPGA/A SIC 的全数字硬件化方案具有全定制性和并行性的 点，为了利用最小 的硬件资源实现指定的系统性能，需要对系统性能指标和实现代价进行 化设计。全数字锁相环 性能指标函数是 化设计的前提，然而其却无法在 s 域内被完备、准确地描述。本文在 z 域内 建立包括峰值时间、调节时间及超调量的全数字硬件化锁相环性能指标函数，指出由于反馈滞后 一拍特性使系统的性能产生退化，然后定量地描述全数字硬件化锁相环的性能指标退化规律。仿 真和实验结果表明峰值时间的退化现象较弱，而调节时间和超调量的退化规律类似，等值线退化 为开口向下的抛物线，使比例、积分系数的耦合加强。 关键词：锁相环;全数字化;硬件化;现场可编程逻辑阵列 中图分类号：TM3 15 Design and Analysis of All-Digital Full-Hardware Phase-Locked Loop L iu Yaj ing,Fan Yu Beij ing Jiaotong University Beij ing 100044 China Abstract The all-digital full-hardware implementation based on field-programmable gate array (FPGA) or application specific integrated circuits(A SIC) has the advantages of high parallelism and full-customer, so the optimization of performance index and cost of implementation is necessary to achieve the specified performance consuming the least resources. The performance indexes of all- digital full-hardware phase-locked loop(PLL) which can not be described in the s domain completely are derived in the z domain firstly, such as peak time, overshoot and setting time, and then this paper points out that one-step-delay in feedback causes the performance degradation, which is studied followed. Simulation and experimental results show that there is no obvious degradation of peak time, but the contour of setting time and overshoot are changed clearly, which strengthen the coupling of the integral and proportional coefficient . Keywords ：Phase-locked loop , all-digital, full-hardwa