parallel computations on pedigree data through mapping to configurable computing devices通过映射到并行计算在谱系数据可配置的计算设备.pdf

Genet. Sel. Evol. 38 (2006) 265–279 265 c INRA, EDP Sciences, 2006 DOI: 10.1051/gse:2006003 Original article Parallel computations on pedigree data through mapping to configurable computing devices ∗ John M. H , Bryce Alvin L FD McMaster Laboratory Chiswick, CSIRO Livestock Industries, Armidale, New South Wales 2350, Australia (Received 16 August 2005; accepted 18 November 2005) Abstract – Pedigree data structures have a number of applications in genetics, including the estimation of allelic or haplotype probabilities in humans and agricultural species, and the es- timation of breeding values in agricultural species. Sequential algorithms for general purpose CPU-based computers are commonly used, but are inadequate for some tasks on large data sets. We show that pedigree data can be directly represented on Field Programmable Gate Arrays (FPGA), allowing highly efficient massively parallel simulation of the flow of genes. Operating on the whole pedigree in parallel, the transmission of genes can occur for all individuals in a sin- gle clock cycle. By using FPGA, the algorithms to estimate inbreeding coefficients and allelic probabilities are shown to operate hundreds to thousands of times faster than the corresponding sequentially based algorithms. Where problems can be largely represented in an