robust and energy-efficient ultra-low-voltage circuit design under timing constraints in 6545 nm cmos健壮和节能超低电压在时间限制在6545纳米cmos电路设计.pdfVIP

J. Low Power Electron. Appl. 2011, 1, 1-19; doi:10.3390/jlpea1010001 OPEN ACCESS Journal of Low Power Electronics and Applications ISSN 2079-9268 /journal/jlpea Review Robust and Energy-Efficient Ultra-Low-Voltage Circuit Design under Timing Constraints in 65/45 nm CMOS David Bol ICTEAM institute, Universit´e catholique de Louvain, Place du Levant 3, Louvain-la-Neuve, Belgium; E-Mail: david.bol@uclouvain.be; Tel.: +32 Fax: +32 Received: 23 November 2010; in revised form: 18 January 2011 / Accepted: 21 January 2011 / Published: 25 January 2011 Abstract: Ultra-low-voltage operation improves energy efficiency of logic circuits by a factor of 10 ×, at the expense of speed, which is acceptable for applications with low-to-medium performance requirements such as RFID, biomedical devices and wireless sensors. However, in 65/45 nm CMOS, variability and short-channel effects significantly harm robustness and timing closure of ultra-low-voltage circuits by reducing noise margins and jeopardizing gate delays. The consequent guardband on the supply voltage to meet a reasonable manufacturing yield potentially ruins energy efficiency. Moreover, high leakage currents in these technologies degrade energy efficiency in case of long stand-by periods. In this paper, we review recently published techniques to design robust an