多输出函数的化简静态冒险.ppt

制作：金燕华 4.5 Timing Hazards 定时冒险 Hazard: when steady-state analysis predicts that the output should not change, a circuit’s output may produce a short pulse (glitch) because of circuit delays. Static Hazards 静态冒险 Static-1 Hazard Static-0 Hazard Static Hazards 静态冒险 For example: F(X,Y,Z)=XZ’+YZ Static Hazards 静态冒险 消除冒险的方法：输出端并接一个滤波电容。 ——增加了输出波形的上升时间和下降时间，使波形变坏。 Finding Static Hazards Using Maps Dynamic Hazard 动态冒险 Chapter 6 Combinational logic Design Practices Documentation Standards Circuit timing MSI combinational logic circuit 6.1 Documentation Standards 结构化的理念 Specification（说明书）：接口及功能描述 Block Diagram（方框图）：主要功能模块及其互联 Schematic Diagram（原理图） Timing Diagram（定时图 ） Structured Logic Device Description（结构化逻辑器件描述） Circuit Description（电路描述）：解释电路内部如何工作 Gate Symbols 门符号 Equivalent Gate Symbols 等效门符号 Signal names and Active Levels Signal Names Signal name should convey associated information. Active Levels for signals active high (高电平有效): EN active low (低电平有效): EN_L Active Levels for Pins Buses 总线 A bus is a collection of two or more related signal lines. (两根或多根相关信号线的集合) Bus name：DATA[31:0]，ADDR[15:0] Representation: (Figure 6-16, 6-1) Additional Schematic Information 附带图示信息 IC Types（IC类型）: 74HCT00 Reference Designators（参考标志）: U1, U2 Pin Number（引脚编号） 6.2 Circuit Timing 6.2 Circuit Timing 6.2 Circuit Timing 6.2 Circuit Timing 6.2 Circuit Timing 6.2 Circuit Timing Homework Supplementary: F1 = ?A,B,C (0,1,3) F2 = ?A,B,C (3,6,7) C AB 00 01 11 10 0 1 1 1 1 C AB 00 01 11 10 0 1 1 1 1 F1 = A’·B’ + A’·C F2 = A·B + B·C Multiple-Output Minimization 多输出函数的化简 We can handle a circuit with n outputs as n independent single-output design problems. A B C F1 F2 A’B’ A’C AB BC Multiple-Output Minimization 多输出函数的化简 F1 = ?A,B,C (0,1,3) F2 = ?A,B,C (3,6,7) C AB 00 01 11 10 0 1 1 1 1 C AB 00 01 11 10 0