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Zhao J, Xu C, Zhang T et al. BACH: A bandwidth-aware hybrid cache hierarchy design with nonvolatile memories. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 31(1): 20–35 Jan. 2016. DOI 10.1007/s11390-016-1609-7 BACH: A Bandwidth-Aware Hybrid Cache Hierarchy Design with Nonvolatile Memories Jishen Zhao 1, Member, ACM, IEEE, Cong Xu 2, Member, ACM, IEEE, Tao Zhang 3, Member, ACM, IEEE and Yuan Xie 4, Fellow, IEEE, Member, ACM 1Department of Computer Engineering, University of California at Santa Cruz, Santa Cruz, CA 95064, U.S.A. 2Hewlet-Packard Labs, Palo Alto, CA 94304, U.S.A. 3NVIDIA Corporation, Santa Clara, CA 95050, U.S.A. 4Department of Electrical and Computer Engineering, University of California at Santa Barbara, Santa Barbara CA 93106, U.S.A. E-mail: jishen.zhao@; cong.xu@; tao.zhang.0924@; yuanxie@ Received September 8, 2015; revised December 10, 2015. Abstract Limited main memory bandwidth is becoming a fundamental performance bottleneck in chip- multiprocessor (CMP) design. Yet directly increasing the peak memory bandwidth can incur high cost and power consump- tion. In this paper, we address this problem by proposing a memory, a bandwidth-aware reconfigurable cache hierarchy, BACH, with hybrid memory technologies. Components of our BACH design include a hybrid cache hierarchy, a reconfigura- tion mechanism, and a statistical prediction engine. Our hybrid cache hierarchy chooses different memory technologies with various bandwidth characteristics, such as spin-transfer torque memory (STT-MRAM), resistive memory (ReRAM), and embedded DRAM (eDRAM), to configure each level so that the peak bandwidth of the overall cache hierarchy is optimized. Our reconfiguration mechanism can dynamically adjust the cache capacity of each level based on the predicted bandwidth demands of running workloads. The bandwidth prediction i