微电子工艺C08NWSPDM01.docVIP

Wuxi Microelectronics Institute 无锡微电子中心第二研究室 ( 中微晶园有限公司 ) 设 计 规 则 （工艺接口文件之一） Tel:0510-5807123-2205 Fax:0510-5807123-3515  0.8um Si-Gate CMOS Single Poly Double Metal Process Outline: Process Features Masking Layers and Process Bias Schematic of Process Flow Design Rules PCM Specification SPICE Parameters Issued by ： Xiao zhiqiang Checked by ： Gao feng Approved by ： Xu zheng 0.8um Si-Gate CMOS Process Wafer Start P Substrate 14-25 ohm-cm Well Formation Nwell Xj = 3.0um Isolation Formation Locos: Birds Beak = 0.3um/side Transistor Gox = 17.5nm N-Channel NLDD, P-Channel PLDD Xj N+ = 0.25um Xj P+ = 0.35um ILD TEOS/BPTEOS 200nm/600nm Metal1 AlSiCu 550nm IMD TEOS/EB/TEOS total:1200nm Metal2 AlSiCu 1100nm Passivation TEOS/PESIN 200nm/1000nm 0.8um Si Gate CMOS SPDM Masking Layers No. Process Sequence Mask Name Digitized Tone Nwell 11 Clean Island 20 Dark N-ch Field 31 Dark Poly 51 Dark N+ S/D 61 Clean P+ S/D 62 Clean Contact 71 Clean Metal1 81 Dark Via 72 Clean Metal2 82 Dark PAD 90 Clean 0.8um Si Gate CMOS SPDM Process Bias No. Process Sequence Bias/Side 1 Nwell 0.0um 2 Island -0.3um * 3 N-ch Field 0.0um 4 Poly 0.025um 5 N+ S/D 0.0um 6 P+ S/D 0.0um 7 Contact 0.0um 8 Metal1 -0.1um 9 Via 0.0um 10 Metal2 -0.1 um 11 PAD 0.0um * Defined on Birds Beak  0.8um Si-Gate CMOS Design Rule 注：以下尺寸皆为最终尺寸 Layer 11 N-well Dimension 11.1 N-well to N-well spacing (same potential) 1.8 11.2 N-well to N-well spacing (different potential) 5.0 11.3 Minimum N-well width 4.0 11.4 N+ island to N-well edge (Inside P-well) 3.5 11.5 P+ island to N-well edge (inside N-well) 3.3 11.6 N+ wel