有关3套练习题答案版last.pptVIP

VHDL程序填空 1、下面程序是一个16位数控分频器的VHDL描述，试补充完整。 __LIBRARY________ IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE _____IEEE.STD_LOGIC_UNSIGNED.ALL _______; ENTITY PULSE16 IS PORT ( CLK : IN STD_LOGIC; LOAD : IN STD_LOGIC; D : IN _STD_LOGIC_VECTOR(15 DOWNTO 0)__; FOUT : OUT STD_LOGIC ); END ENTITY; __ARCHITECTURE ___ one OF PULSE16 IS SIGNAL FULL : STD_LOGIC; BEGIN P_REG: PROCESS(CLK) Variable___ CNT16 : STD_LOGIC_VECTOR(15 DOWNTO 0); BEGIN IF CLKEVENT AND CLK = 1 THEN IF _______load=’1’_____ THEN -- LOAD高电平置数 CNT16 :