vhdl硬件描述语言主课件.ppt

ARCHITECTURE behave OF cnt_updwn IS BEGIN PROCESS ( clk, clr ) BEGIN IF ( clr = 1 ) THEN count = ( others = ’0’ ); ELSIF ( clkevent and clk = 1 ) THEN IF ( load = 1 ) THEN count = data ; ELSIF ( updown = 1 ) THEN count = count + 1; ELSE count = count - 1; END IF; ? ? END IF; END PROCESS; END behave; （4）60进制BCD码计数器 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; ENTITY bcd_cnt_60 IS PORT ( clk, clr : IN std_logic; load, en : IN std_logic; data : IN std_logic