数字频率计硬件设计(转载).docVIP

简易数字频率计硬件设计（转载） 摘要 在当今社会，随着电子计算机计算机、通讯设备、音频视频等是一种基本的测量仪器，是用数字显示被测信号频率的仪器，被测信号可以是正弦波，方波或其它周期性变化的信号。因此，它被广泛应用与航天、电子、测控等领域。它的基本测量原理是，首先让被测信号与标准信号一起通过一个闸门，然后用计数器计数信号脉冲的个数，把标准时间内的计数的结果，用锁存器锁存起来，最后用显示译码器，把锁存的结果用LED数码显示管显示出来。实际的硬件设计用到的器件较多，连线比较复杂，而且会产生比较大的延时，造成测量误差、可靠性差。随着复杂可编程逻辑器件（CPLD）的广泛应用，以EDA工具作为开发手段，运用VHDL语言，将使整个系统大大简化， 提高整体的性能和可靠性。AT89C51的测频系统该装置由输入部分与显示部分组成，输入部分可以收到发射机送来的信号，并通过单片机再传到显像管。此系统具有测量频率和带宽等功能。 关键词：频设计的率计，直接侧频法，间接测频法，单片机AT89C51 Simple digital frequency meters hardware design Abstract In the society, along with the electronic accounting machine computer, the communication equipment, the audio frequency video frequency and so on use, the frequency meter also more and more frequent is used now, frequency meters development also becomes especially important. The frequency meter is one kind of basic metering equipment, is with the digit demonstrated that was measured the signaling frequency the instrument, was measured the signal may be the sine wave, the square-wave or other periodic variation signal. Therefore, it is widely applied and domains and so on astronautics, electron, observation. Its preliminary survey principle is, first lets measure that the signal and the standard signal through a strobe, then with the counter counting signal pulses integer, standard times in countings result, save together with the latch lock, finally uses to demonstrate the decoder, saves the result the lock to demonstrate with the LED numerical code display tube. The component which uses in the hardware design in fact are many, the segment is also quite complex, will have the quite big time delay, will cause the measuring error, the reliability to be bad. Along with complex programmable logical component (CPLD) the widespread application, takes the development method by the EDA tool, utilizes the VHDL language, will cause the overall system big simplification, enhances the whole the performance and the reliability. The digital frequency meter is one of most basic parameters,