Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design-准确和简化的预测AVF的延迟和节能的高速缓存设计.pdfVIP

Ma AG, Cheng Y, Xing ZC. Accurate and simplified prediction of AVF for delay and energy efficient cache design. JOURNAL OF COMPUTER SCIENCE AND TECHNOLOGY 26(3): 504–519 May 2011. DOI 10.1007/s11390-011-1150-7 Accurate and Simplified Prediction of AVF for Delay and Energy Efficient Cache Design An-Guo Ma ( ), Yu Cheng ( ), and Zuo-Cheng Xing ( ), Senior Member, CCF School of Computer Science, National University of Defense Technology, Changsha 410073, China E-mail: {anguo.ma, y.cheng, zc.xing}@ Received January 5, 2011; revised April 2, 2011. Abstract With continuous technology scaling, on-chip structures are becoming more and more susceptible to soft errors. Architectural vulnerability factor (AVF) has been introduced to quantify the architectural vulnerability of on-chip structures to soft errors. Recent studies have found that designing soft error protection techniques with the awareness of AVF is greatly helpful to achieve a tradeoff between performance and reliability for several structures (i.e., issue queue, reorder buffer). Cache is one of the most susceptible components to soft errors and is commonly protected with error correcting codes (ECC). However, protecting caches closer to the processor (i.e., L1 data cache (L1D)) using ECC could result in high overhead. Protecting caches without accurate knowledge of the vulnerability characteristics may lead to over-protection. Therefore, designing AVF-aware ECC is attractive for designers to balance among performance, power and reliability for cache, especially at early design stage. In this paper, we improve the methodology of cache AVF computation and develop a new AVF estimation framework, soft error reliability analysis based on SimpleScalar. Then we characterize dy