基于FPGA技术的8位模型机设计与实现-南昌航空大学期刊网.PDFVIP

21 FPGA 8 q (, 330063) []; FPGA; EDA [ ] EDA FPGA 8, , Quartus Ò 610, SOPC /EDA , [] TP3681 1 [] A [] 1001- 49 6( 010) 03- 00 1- 06 D esign and Im p lem entation of an 8- b it M odel Com pu ter Based on FPGA ZHANG Sheng HU Jian- m in CHA IH ong FU La (N anchang H ang kong Un iv er sity, N anchang, J iangx i 330063, Ch ina ) K ey w ord s: design of m odel computer; FPGA; EDA A bstract: A smi ple 8- b it m odel com puter is designed and mi p lem ented w ith EDA technology in FPGA chip, including instruction system, calcu lator, controller, m emory, tmi ing generator and the bus. It is designed, com piled and smi u lated under the Integrated Developm ent Environm ent of Quartus II 6. 0, finally down loaded to the SOPC / EDA expermi en tal p latform for un its and system tes- ting. The expermi ent resu ltm eets the design requ irements. , ( F ield Programmable ALU GateA rray, FPGA)CPU , , VHDL , , , CPU , 1 CPU ( 8005180086) (ARMExcalibue FPGA ) 8 1 (N ios), FPGA , : SOC( System On a Chip) SOPC( System On a Programm able Ch ip ) /, , CPU , , CPU , CPU EDA FPGA 8 [] 010- 08- 0 [] 010- 09- 06 [] 张 胜( 1968- ), 男,南昌航空大学信息工程学院副教授, 博士主要研究方向: 数据挖掘GPS /GISW eb信息处理 线传感器网络 010年 9月 22 第 4卷 第 3 期 基于 FPGA技术的 8位模型机设计与实现 ALU, DR0DR1, R0 MEMORAY, IR, LC, ~ R , PC, AR, / INPUT OUTPUT 图 1 8位模型机的逻辑结构 1. 1 ( ALU ) 1. 3 ( ALU ) , , / 0/ 0/ 0 , 4 D 74LS181VHDL 1. 4 1.