超敏电流计-AdvancedSiliconDeviceandProcessLab.PPTVIP

Single-Electron Transistor(SET) 台大機械所碩二 許世瑋 What is SET? Island 可為金屬或半導體材料 The charging energy should be larger than thermal energy--preventing the effect of thermal energy. EC=e2/2CΣkBT (determine operation temp) The tunneling junction resistance should be larger than typical value Rjh/ e2~25K? (Room temp. test) Coulomb Blockade (CB) Transport in SET Single-electron MOS 單電子半場效電晶體 (Minnesota Uni.) Single-electron MOS Self-aligned Floating Dot Gate—Fabrication Process Coulomb Blockade (CB) Transport in SET Quantum Confinement Energy Materials of High-Ea Island With Ea beyond ~100mev, exhibit noticeable Coulomb blockade oscillations at RT Fabrication Method–V-PADOX A Si wire with a fine trench across it on a SOI substrate. Thermal oxidation is carried out just after the wire with a fine trench is defined. Fabrication Process Trench formation Wire and side-gate definition Top-gate definition Comparison Twin Island Wire width (a),(b)=60nm (c)=160nm 由於熱應力的關係使得edge附近的oxidation rate減慢造成twin island 形成island無需經過lithography definition的步驟 STM/AFM Nano-oxidation Process 控制cantilever和Ti薄膜之間的電壓可以改變TiOx的厚度（width of island） STM/AFM Nano-oxidation Vb=6~10V(high bias) 電流主要是F-N tunneling，比較不受溫度的影響 Vb=0.1~1V(low bias) 由於溫度產生thermion emission current造成電流有很大的變化(steep slope) Temperature Dependence(10nm) Weak temperature dependence Structure of SET(Ti) Coulomb gap~50mV CNT-SET @ RT AU 電極 CNT-SET @ 260K @ 30K 每個方塊的電子數目是固定的,可用Vg來控制電子進入island Criteria For A good Single-electron Tunneling Memory 操作溫度需在室溫（300K）,或者至少能在液態氮的溫度（77K）並能有適當的bit error rate. Low power consumption 相同的讀、寫時間且循環時間短 Application Nonvolatile Random-Access Memory (NOVORAM) Application Single-electron Transistor Scanning Electrometer(SETSE) Application Single-electron Transistor Scanning Electrometer(SETSE) Application Single-electron Transistor Scanning Electrometer(SETSE) Application e/Cs隨著tip接近表面而驟減 Bias Voltage~0.6V,減少SET和sample間的功函數差,如此可避免因tip產生的電場的干擾 Applicati