现代CMOS工艺基本流程培训.pptVIP

* Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 IMD抛光 IMD抛光 CMP * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 IMD1 Photoresist 光刻胶成形 光刻胶成形 用于定义通孔(Vias) * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BPSG W Contact Plug Metal1 Photoresist IMD1 通孔刻蚀 通孔刻蚀 基于氟的RIE，获得垂直的侧墙 提供金属层之间的连接 * Silicon Substrate P+ Silicon Epi Layer P- P- Well N- Well N+ Drain N+ Source P+ Drain P+ Source BP