计算机设计与实践——32位ALU设计.pptxVIP

32位ALU设计——Verilog HDL语言module alu(alu_da,alu_db,alu_clt,alu_shift,alu_zero_out,overflow_out,alu_dc );input [31:0]alu_da;input [31:0]alu_db;input [3:0]alu_clt;input [4:0]alu_shift;output reg alu_zero_out;output reg overflow_out;output reg [31:0]alu_dc;wire alu_zero;wire overflow;wire [31:0]alu_and;//与结果wire [31:0]alu_or;//或结果wire [31:0]alu_xor;//异或结果reg [31:0]alu_sll;//左移结果reg [31:0]alu_srl;//右移结果reg [31:0]alu_sra;//算数右移wire [31:0]alu_add;//加减运算结果wire c2;//加法器进位输出reg Sub;//加法器控制端wire [31:0]alu_db_n;//b取非运算reg [31:0]alu_db_mux;//b的加减选择运算wire ci;//进位输出always@(*)begin case(alu_clt) 0:alu_dc=alu_an