二输入与非门、或非门版图设计.doc

课程名称 Course 集成电路设计技术 项目名称 Item 二输入与非门、或非门版图设计 与非门电路的版图： .spc文件（瞬时分析）： * Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ; * TDB File: E:\cmos\yufeimen, Cell: Cell0 * Extract Definition File: C:\Program Files\Tanner EDA\L-Edit\spr\morbn20.ext * Extract Date and Time: 05/25/2011 - 10:03 .include H:\ml2_125.md VPower VDD GND 5 va A GND PULSE (0 5 0 5n 5n 100n 200n) vb B GND PULSE (0 5 0 5n 5n 50n 100n) .tran 1n 400n .print tran v(A) v(B) v(F) * WARNING: Layers with Unassigned AREA Capacitance. * Poly Resistor * Poly2 Resistor * N Diff Resistor * P Diff Resistor * N Well Resistor * P Base Resistor * WARNING: Layers with Unassigned FRINGE Capacitance. * Pad Comment * Poly Resistor * Poly2 Resistor * N Diff Resistor * P Diff Resistor * N Well Resistor * P Base Resistor * Poly1-Poly2 Capacitor * WARNING: Layers with Zero Resistance. * Pad Comment * Poly1-Poly2 Capacitor * NMOS Capacitor * PMOS Capacitor * NODE NAME ALIASES * 1 = VDD (34,37) * 2 = A (29.5,6.5) * 3 = B (55.5,6.5) * 4 = F (42.5,6.5) * 6 = GND (25,-22) M1 VDD B F VDD PMOS L=2u W=9u AD=99p PD=58u AS=54p PS=30u * M1 DRAIN GATE SOURCE BULK (47.5 14.5 49.5 23.5) M2 F A VDD VDD PMOS L=2u W=9u AD=54p PD=30u AS=99p PS=58u * M2 DRAIN GATE SOURCE BULK (39.5 14.5 41.5 23.5) M3 F B 5 GND NMOS L=2u W=9.5u AD=52.25p PD=30u AS=57p PS=31u * M3 DRAIN GATE SOURCE BULK (47.5 -18 49.5 -8.5) M4 5 A GND GND NMOS L=2u W=9.5u AD=57p PD=31u AS=52.25p PS=30u * M4 DRAIN GATE SOURCE BULK (39.5 -18 41.5 -8.5) * Total Nodes: 6 * Total Elements: 4 * Extract Elapsed Time: 0 seconds .END 与非门电路仿真波形图（瞬时分析）： .spc文件（直流分析）： * Circuit Extracted by Tanner Researchs L-Edit V7.12 / Extract V4.00 ; * TDB File: E:\cmos\yufeimen, Cell: Cell0 * Extract Definition File: C:\Program Files\Tanner EDA\L-Edit\spr\morbn20.ext * Extract Date and Time: 05/25/2011 - 10:03 .include H:\ml2_125.md VPower VDD GND 5 va A GND 5 vb B GND 5 .dc va 0 5 0.02 vb 0 5 0.