实验5 时序逻辑电路实验.doc

实验5 时序逻辑电路实验 1.设计一个完整的时序逻辑电路，并用MAXPLUS进行仿真，将结果下载到实验箱中，测试电路的正确性。 要求：设计一个24进制计数电路，数字显示在数码管上，有手动和自动两种模式，在自动模式下每隔1秒从00显示到23然后循环，在手动模式下，每按一次按键计数值加1。每次从23跳到00时，响铃提示。 应包含VHDL源程序，详细的设计报告，对程序，仿真结果，实验箱运行结果（图片贴到报告中）进行详尽的分析 24进制器（很重要） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY hours24 IS PORT(CLK,X:IN STD_LOGIC; O_1:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); O_2:OUT STD_LOGIC_VECTOR(3 DOWNTO 0); W:OUT STD_LOGIC; bee:OUT STD_LOGIC ); END hours24; ARCHITECTURE g3 OF hours24 IS SIGNAL COUNT_1,COUNT_2:STD_LOGIC_VECTOR(3 DOWNTO 0); BEGIN PROCESS(CLK,X) BEGIN IF(CLKEVENT AND CLK = 1 )THEN IF(COUNT_2=2 AND COUNT_1=3)THEN COUNT_2=0000; COUNT_1=0000; bee=1; ELSIF(COUNT_1=9)THEN COUNT_2=COUNT_2+1; COUNT_1=0000; ELSE COUNT_2=COUNT_2; COUNT_1=COUNT_1+1;bee=0; END IF; END IF; END PROCESS; W=X; O_2=COUNT_2 ; O_1=COUNT_1; END g3; 分频（重要） LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_unsigned.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY fenpin IS PORT(clk:IN STD_LOGIC; sd:IN STD_LOGIC; EN:IN STD_LOGIC; clk_F:OUT STD_LOGIC; sd_1:OUT STD_LOGIC; wx:OUT STD_LOGIC; EN_1:OUT STD_LOGIC ); END fenpin; ARCHITECTURE g1 OF fenpin IS SIGNAL clk_DIV:STD_LOGIC; BEGIN PROCESS(clk) VARIABLE COUNT:INTEGER RANGE 0 TO 4; BEGIN IF(clkEVENT AND clk = 1)THEN IF(COUNT=3)THEN COUNT:=0; ELSE COUNT:=COUNT+1; IF( COUNT2)THEN clk_DIV= 1; ELSE clk_DIV = 0; END IF; END IF; END IF; END PROCESS; clk_F=clk_DIV; EN_1=EN; sd_1=sd; wx=clk; END g1; 按键消除抖动（重要） library IEEE; use ieee.std_logic_1164.all; entity xiaodou is port( clk,key,xuan: in std_logic; dmc,clk_out,xuan_out: out std_logic ); end xiaodou; architecture g0 of xiaodou is signal r,s,qr,qs,d1,d2,q1,q2,d3,d4,q3,q4,cp:std_logic; begin process(clk) begin if(clkevent and clk=1)then d1=key; d2=d1; q2=d2; d3=qr; d