A Low Jitter Pll Clock Generator For Microprocessors With Lo外语英文电子书.pdfVIP

IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 34, NO. 4, APRIL 1999 513 A Low-Jitter PLL Clock Generator for Microprocessors with Lock Range of 340–612 MHz David W. Boerstler Abstract— A fully integrated, phase-locked loop (PLL) clock II. INTRODUCTION generator/phase aligner for the POWER3 microprocessor has been designed using a 2.5-V, 0.40-m digital CMOS6S process. This paper describes a fully integrated PLL-based clock The PLL design supports multiple integer and noninteger fre- generator/phase aligner used for the POWER3 microprocessor. quency multiplication factors for both the processor clock and The microprocessor is fabricated in IBM CMOS6S technology an L2 cache clock. The fully differential delay-interpolating and contains approximately 12 million transistors. With the mi- voltage-controlled oscillator (VCO) is tunable over a frequency croprocessor actively executing instructions, this PLL achieved range determined by programmable frequency limit settings, enhancing yield and application flexibility. PLL lock range for cycle–cycle jitter of 10.0 ps rms, 80 ps P-P in its application the maximum VCO frequency range settings is 340–612 MHz. environment and 8.4 ps rms, 62 ps P-P with the microprocessor The charge-pump current is programmable for additional control in a reset state with a portion of the clock tree active. of the PLL loop dynamics. A differential on-chip loop filter with A simplified block diagram of the PLL clock generator is common-mode correction improves noise rejection. Cycle–cyc