Low Power Data Forwarding For Vliw Embedded Architectures外语英文电子书.pdfVIP

614 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 5, OCTOBER 2002 Low-Power Data Forwarding for VLIW Embedded Architectures Mariagiovanna Sami, Senior Member, IEEE, Donatella Sciuto, Member, IEEE, Cristina Silvano, Member, IEEE, Vittorio Zaccaria, Student Member, IEEE, and Roberto Zafalon Abstract—In this paper, we propose a low-power approach to sign techniques are widely adopted during microprocessor de- the design of embedded very long instruction word (VLIW) pro- sign to meet the stringent power constraints, while avoiding per- cessor architectures based on the forwarding (or bypassing) hard- formance degradations. For high-performance processors, such ware, which provides operands from interstage pipeline registers directly to the inputs of the function units. The power optimiza- as VLIW, some low-power solutions target the reduction of the tion technique exploits the forwarding paths to avoid the power effective switched capacitance of each logic gate. The effective cost of writing/reading short-lived variables to/from the register switched capacitance of a logic gate is defined as the product file (RF). Such optimization is justified by the fact that, in appli- of the load capacitance at the output of the gate and its output cation-specific embedded systems, a significant number of vari- switching activity. ables are short-lived, that is, their liveness (from first definition to last use) spans only few instructions. Values of short-lived vari- While the reduction of the effective switched capacitance is ables can thus be accessed directly through the forwarding regis- suitable for the combinational and in-core sequential part of