Lab1_体系结构实验报告.docVIP

2012年3月1日 实验目的和要求 understand the principles of ALU and master methods of ALU design understand the principles of ALU controller and master methods of ALU controller design understand the principles of register file and master methods of register file design so the task is first, design a ALU with ALU controller then, design a register file 实验内容和原理 2.1 ALU with ALU controller We input the operand r, s; both are 32 bit integer, and aluc is the control code that defines the operation. So we just make the code block, totally as ALU block, ALUC block, display block. Figure 1 the input and output diagram Figure 2 ALU operations Figure 3 the truth table of operation code Figure 4 principle of ALU 2.2 register file The process is similar to the 2.1, when we get the principle of register file , it can be easily coding. Figure 5 the input and output Figure 6 The Circuit Integrating ALU 实验过程和数据记录 ALU and ALU Controller Here is the code: Top block: module ALUC(input CCLK, input [1:0]BTN, input [3:0] SW, output LCDRS, LCDRW, LCDE, output [3:0] LCDDAT,output LED); wire [3:0] lcdd; wire rslcd, rwlcd, elcd; wire o_zf; wire [31:0] o_alu; wire [2:0] i_aluc; wire [1:0] alu_op; wire [3:0] func; reg [31:0] o_alu_old; reg [255:0] strdata; reg [31:0] i_r; reg [31:0] i_s; reg rst; assign LCDDAT[3] = lcdd[3]; assign LCDDAT[2] = lcdd[2]; assign LCDDAT[1] = lcdd[1]; assign LCDDAT[0] = lcdd[0]; assign LCDRS = rslcd; assign LCDRW = rwlcd; assign LCDE = elcd; assign LED = o_zf; assign func[0] = SW[0]; assign func[1] = SW[1]; assign func[2] = SW[2]; assign func[3] = SW[3]; assign alu_op[0] = BTN[0]; assign alu_op[1] = BTN[1]; initial begin strdata = 1111 2222 ; i_r = 32h1111; i_s = 32h2222; rst = 0; o_alu_old = 0; end display M0 (CCLK, rst, strdata, rslcd, rwlcd, elcd, lcdd);