基于Matlab和EDA工具的数字滤波器(实验).pptVIP

* * * * * * Preface xiii Acknowledgments xv 1. Architecting Speed 1 1.1 High Throughput 2 1.2 Low Latency 4 1.3 Timing 6 1.3.1 Add Register Layers 6 1.3.2 Parallel Structures 8 1.3.3 Flatten Logic Structures 10 1.3.4 Register Balancing 12 1.3.5 Reorder Paths 14 1.4 Summary of Key Points 16 2. Architecting Area 17 2.1 Rolling Up the Pipeline 18 2.2 Control-Based Logic Reuse 20 2.3 Resource Sharing 23 2.4 Impact of Reset on Area 25 2.4.1 Resources Without Reset 25 2.4.2 Resources Without Set 26 2.4.3 Resources Without Asynchronous Reset 27 2.4.4 Resetting RAM 29 2.4.5 Utilizing Set/Reset Flip-Flop Pins 31 2.5 Summary of Key Points 34 3. Architecting Power 37 3.1 Clock Control 38 3.1.1 Clock Skew 39 3.1.2 Managing Skew 40 3.2 Input Control 42 3.3 Reducing the Voltage Supply 44 3.4 Dual-Edge Triggered Flip-Flops 44 3.5 Modifying Terminations 45 3.6 Summary of Key Points 46 4. Example Design: The Advanced Encryption Standard 47 4.1 AES Architectures 47 4.1.1 One Stage for Sub-bytes 51 4.1.2 Zero Stages for Shift Rows 51 4.1.3 Two Pipeline Stages for Mix-Column 52 4.1.4 One Stage for Add Round Key 52 4.1.5 Compact Architecture 53 4.1.6 Partially Pipelined Architecture 57 4.1.7 Fully Pipelined Architecture 60 4.2 Performance Versus Area 66 4.3 Other Optimizations 67 5. High-Level Design 69 5.1 Abstract Design Techniques 69 5.2 Graphical State Machines 70 5.3 DSP Design 75 5.4 Software/Hardware Codesign 80 5.5 Summary of Key Points 81 6. Clock Domains 83 6.1 Crossing Clock Domains 84 6.1.1 Metastability 86 6.1.2 Solution 1: Phase Control 88 6.1.3 Solution 2: Double Flopping 89 6.1.4 Solution 3: FIFO Structure 92 6.1.5 Partitioning Synchronizer Blocks 97 6.2 Gated Clocks in ASIC Prototypes 97 6.2.1 Clocks Module 98 6.2.2 Gating Removal 99 6.3 Summary of Key Points 100 End Thanks everyone! * * * * * * * * * * * * * * * * * * * * * * * * * * * * Advanced Example FPGA design techniques for a FIR filter Outline constant coefficient FIR filter IP based design flow optimizatio