功率评估软体简介.pptVIP

* PowerMixerIP: IP-Level Power Modeling for Processors Shan-Chien Fang1 Jia-Lu Liao2 Chen-Wei Hsu2 Chia-Chien Weng2 Shi-Yu Huang2 Wen-Tsan Hsieh3 Jen-Chieh Yeh3 1TinnoTek Inc, Taiwan (service@.tw) 2Dept. of Electrical Engineering, National Tsing Hua University, Taiwan 3Industrial Technology Research Institute, Taiwan Introduction Power dissipation has become a major design metric IR drop, signal integrity power budgeting, power tradeoff, battery lifetime power grid design, thermal analysis, packaging High-level power estimation enable power optimization in early stage achieve higher power saving fast but often suffer from inadequate accuracy PowerMixerIP IP-based power modeling/analysis tool bottom-up power modeling/analysis methodology fast and accurate power analysis for large SoC designs Power Modeling Strategies Processor Model General IP Model PowerMixerIP For general IP Adopt operation-mode-based model By observing user-defined operation mode and key signals Specific for processor Adopt instruction-level or stage-accurate model By observing the program counter register and the instruction registers IP-Based Power Simulation μProcessor (3) Essential VCD (1) SoC Netlist (2) IP Power Models (.PMF) Cache Bus DMA ASICs …… (4) Std. Cell Power Library PowerMixerIP (IP-Based Power Simulation) Power Profile PowerMixerIPcan significantly speed up the simulation process! Processor Modeling Example:PAC-DSP Core Architecture PACDSP core is a VLIW processor with 8 pipeline stages and 5 issues ISA supports 206 instructions Energy Model Complexity Enumerate all possible instruction combinations 206 is total number of instruction 5 is number of instructions per issue O(2065) Divide all instructions into instruction classes instructions with similar behaviors in one class divide instructions into 13 types O(2065)?O(135) Sum up the individual power of each instruction in a issue O(135)?O(13) Consider power consumption of an instruction in