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PIPELINED PROCESSOR CARRYING OUT BRANCH PREDICTION BY BTB BACKGROUND OF THE INVENTION1. Field of the InventionThe present invention relates to pipelined processors, and more particularly, to a pipelined processor carrying out branch prediction using hardware called a branch target buffer (hereinafter referred to as a BTB).2. Description of the Background ArtIn a pipelined processor, performance improvement is mainly hampered by disorder of a pipeline due to branch (branch penalty). In order to reduce this branch penalty, branch prediction is introduced in an ordinary pipelined processor.One system of branch prediction uses hardware called a BTB. In this system, information required for prediction is held in the BTB. and branch prediction is carried out in the following procedure.(1) Registration/UpdateWhen a branch instruction is executed, an execution result of the branch instruction such as a branch target address and a branch direction is registered in a BTB entry addressed by the lowermost several bits of an instruction address of the branch instruction, or updated.(2) PredictionWhen an instruction fetch is to be carried out, the BTB is simultaneously accessed at the same address as that with which an instruction cache is accessed. In this case, the BTB is addressed by the lowermost several bits used in the above (1). If history information on an effective instruction is registered at the relevant address of the BTB.a branch direction is predicted based on the history information. In this case, if it is predicted that a branch will be taken, a branch target address is set in a program counter (PC).(3) Prediction CheckWhen the branch instruction is executed, the execution result and the branch prediction are verified to check the prediction. When the prediction is erroneous, instructions which have been fed to the pipeline during the period from fetch of the branch instructions to completion of execution of the branch instructions are invalidated, and a correct i