16阶FIR滤波器verilogHDL代码.docVIP

16阶FIR滤波器verilogHDL代码 //----------------------- // module description //----------------------- module fir( //input din, clock, reset, // dout ); //----------------------- // port declaration //----------------------- input [7:0] din; input clock; input reset; output [16:0] dout; //----------------------------------------------------- // signal declaration //----------------------------------------------------- reg [7:0] din_reg_00_8b; //移位寄存器 reg [7:0] din_reg_01_8b; reg [7:0] din_reg_02_8b; reg [7:0] din_reg_03_8b; reg [7:0] din_reg_04_8b; reg [7:0] din_reg_05_8b; reg [7:0] din_reg_06_8b; reg [7:0] din_reg_07_8b; reg [7:0] din_reg_08_8b; reg [7:0] din_reg_09_8b; reg [7:0] din_reg_10_8b; reg [7:0] din_reg_11_8b; reg [7:0] din_reg_12_8b; reg [7:0] din_reg_13_8b; reg [7:0] din_reg_14_8b; reg [8:0] sum_0_9b; //预相加结果 reg [8:0] sum_1_9b; reg [8:0] sum_2_9b; reg [8:0] sum_3_9b; reg [8:0] sum_4_9b; reg [8:0] sum_5_9b; reg [8:0] sum_6_9b; reg [8:0] sum_7_9b; wire [24:0] mult_0_25b; //乘法结果 wire [24:0] mult_1_25b; wire [24:0] mult_2_25b; wire [24:0] mult_3_25b; wire [24:0] mult_4_25b; wire [24:0] mult_5_25b; wire [24:0] mult_6_25b; wire [24:0] mult_7_25b; reg [27:0] mult_0_28b; //乘法结果 reg [27:0] mult_1_28b; reg [27:0] mult_2_28b; reg [27:0] mult_3_28b; reg [27:0] mult_4_28b; reg [27:0] mult_5_28b; reg [27:0] mult_6_28b; reg [27:0] mult_7_28b; reg [27:0] temp_1lev_1; //流水线加法寄存结果 reg [27:0] temp_1lev_2; reg [27:0] temp_1lev_3; reg [27:0] temp_1lev_4; reg [27:0] temp_2lev_1; reg [27:0] temp_2lev_2; reg [27:0] last_result; wire [15:0] dout; parameter [15:0] h0_16b = 16h0000; //抽头系数 parameter [15:0] h1_16b = 16h0065; parameter [15:0] h2_16b = 16h018F; parameter [15:0] h3_16b = 16h035A; par