1 超高速CMOS 动态负载分频器设计及研究邓文娟1 雷鑑铭2 朱兆优1 （东.pdfVIP

超高速 CMOS动态负载分频器设计及研究 邓文娟 1 雷鑑铭 2 朱兆优 1 （东华理工大学电子与机械工程学院，3440001 2 华中科技大学电子科学与技术系，430074 ） 摘要：在比较反转触发器（TFF ）的各种结构的基础上，给出了一种单时钟信号控制实现超 高速分频的电路结构，以及具体设计过程。分频器使用动态负载，输出两路互补信号。采用 SMIC 0.18 ｕm 1P6M CMOS工艺，在电源电压为1.8 V的情况下，仿真实现了工作速度10 GHz(可工作频率范围为1～13.5 GHz)、功耗仅为3.1 mW的二分频器，可用于超高速锁相环、 时钟数据恢复设计中。 关键词：CMOS分频器；反转触发器；单时钟信号；动态负载。 中图分类号： TN4 文献标识码：A Design and Research of Super-high Speed Dynamic Frequency divider 1 2 1 DENG Wen-juan , LEI Jian-ming ，ZHU Zhao-you (Department of Electronic Mechanical Engineering, East China Institute of Technology, 1 344000) (Department of Electronic Science Technology, Huazhong University of Science and 2 Technology, 430074) Abstract: On the basis of comparing to each kind of structure of toggle flip-flop(TFF),a super-high speed frequency divider circuit structure and it’s specific design process is presented, which controlled by single clock signal to achieve. The divider output two channels of complementary signals, with dynamic load. Based on SMIC 0.18 ｕm 1P6M CMOS, the device is simulated with software of Cadence-Spectre. Simulation shows that, with a 1.8V supply voltage, the frequency divider operates well in the frequency range from 1GHz to 13.5GHz, only 3.1mW power consumption.This frequency divider can be used to the circuit design of high speed phase-locked loop and clock and data recovery 。 Key: CMOS frequency divider; Toggle flip-flop; Single clock signal controlling; Dynamic loading. 0. 引言 分频电路在频率合成、光纤通信、无线通信等系统中有着广泛应用。在高速通讯系统中， 当数据传输速率达到或超过10G