Array工艺过程DGL.ppt

Array工艺技术 目录 1·Array工艺构成流程 2· 5Mask工艺流程 3· 4Mask工艺流程 3.1 Gate process 3.2 SDT process 3.3 PVX process 3.4 ITO process 4· 4Mask5Mask工艺比较 4Mask工艺流程--简介 与传统的5mask工艺不同，4mask工艺并没有按顺序依次进行5层的Thinfilm，mask，etch，strip。而是将multi层与S/D层一起沉积，涂覆PR胶后进行一次mask，利用光栅或半透膜，使中心光照度减小，在PR胶上形成一个凹坑，显影后，用干刻击碎PR胶使其整体变薄，露出S/D层，接着干刻击穿S/D层进行Ashing至Multi层的一部分。然后进行剥离。同时完成这两层的全过程。从而减少一步mask过程，减少时间，降低了成本。 品质、速度、团队 Page * Six sigma for working smarter Page * 品质/客户服务部 for working Smarter BOEOT QA/OQA 董国梁 2009 . 03 . 15. Array工艺构成 Photo Resist Thin Film Glass Exposure Light Photo Mask Strip Thin Film Glass PR coating Photo Resist Develop Etch Mask工艺流程 沉积 清洗 PR涂附 曝光 显影 刻蚀 PR剥离 检查 Wet Etch Dry Etch 5Mask工艺流程 Glass Glass Gate Metal Deposition Gate Patterning SiNx Deposition i a-Si Deposition n+ a-Si Deposition Active Patterning Data Metal Deposition Data Metal Patterning n+ a-Si Etch SiNx Deposition Via Hole Patterning ITO Deposition Pixel Patterning Pixel Data Passivation SiNx n+ a-Si i a-Si Gate insulator SiNx Gate Via hole 5Mask工艺流程 AFST01 AFST08 AFST04 AFST03 AFST02 AFST09 AFST11 AFST12 AFST14 AFST10 AFST07 A3 A1 A2 AFST13 AFST15 AFST18 EV ATGT01 AEWS07 [GA] AEWE01 [GATE] ATIC01 AEWE07 [ITO] ATSP02 [GATE] ATPC01 ATSP06 [ITO] ATPE02 [VIA] APEX01 ATPK01 [GATE] AEWE04 [S/D] ATPE05 [VIA] AEDE01 [ACT] ATPE01 [VIA] ATPE04 [ACT] ATPE03 [ACT] ATPE06 [ACT] ATPE07 [ACT] ATPE08 [ACT] APEX02 ATPK02 [GATE] ATSP07 [ITO] ATSP08 [ITO] ATSP01 [GATE] ATSP03 [GATE] ATSP04 [S/D] ATSP05 [S/D] APEX03 APEX04 APEX05 APEX06 APEX07 APEX08 APEX09 APEX010 APEX011 APEX012 AEDE10 [VIA] AEDE08 [VIA] ATPK03 [GATE] ATPK04 [ACT] ATPK05 [ACT] ATPK06 [S/D] ATPK07 [S/D] ATPK [S/D] ATPK10 [ITO] ATPK09 [ITO] ATPK11 [ITO] ATPK12 [ITO] AEDE09 [VIA] AEWE02 [GATE] AEWE03 [GATE] AEWS08 AEWS09 AEDE05 [N+] AEWS01 AEWS02 AEWS03 AEWS04 AEWE08 [ITO] AEWE05 [S/D] AEWE06 [S/D] AEWS05 AEDE02 [ACT] AEDE06 [N+] AEWE09 [ITO] AEDE03 [ACT] AEDE07 [N+] 02 02 ATPC03 ATPC04 AMCD01 AMCD02 AMAF01 AMMA01 AM4P01 ATAN01 ATAN02 AM