第7章有限状态机.ppt

7.2 Moore型有限状态机的设计 7.2 Moore型有限状态机的设计 7.2 Moore型有限状态机的设计 * LPM_ROM定制, 命名sindata.vhd File - MegaWizard Plug-In Manager Create a new custom megafunction variation(变异) Storage- LPM_ROM-VHDL- directory \sindata.vhd Q: 数据位宽度8 address:地址线宽为6 ROM中初始化文件sindata.mif，采用相对路径． * LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY sindata IS PORT (address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END sindata; ARCHITECTURE SYN OF sindata IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); COMPONENT lpm_rom GENERIC ( lpm_width : NATURAL; lpm_widthad : NATURAL; lpm_address_control : STRING; lpm_outdata : STRING; lpm_file : STRING ); * PORT (address : IN STD_LOGIC_VECTOR (5 DOWNTO 0); inclock : IN STD_LOGIC ; q: OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END COMPONENT; BEGIN q = sub_wire0(7 DOWNTO 0); lpm_rom_component : lpm_rom GENERIC MAP ( LPM_WIDTH = 8, LPM_WIDTHAD = 6, LPM_ADDRESS_CONTROL = REGISTERED, LPM_OUTDATA = UNREGISTERED, LPM_FILE = sin_data.mif“ ) PORT MAP ( address = address, inclock = inclock, q = sub_wire0 ); END SYN; * 仿真结果： * 6.6.1 LPM_FIFO模块 FIFO: first in first out File - MegaWizard Plug-In Manager Create a new custom megafunction variation(变异) Storage- LPM_FIFO-VHDL- directory \fifo2.vhd 数据位宽度8 ，数据深度512 * LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY fifo2 IS PORT(data : IN STD_LOGIC_VECTOR (7 DOWNTO 0); wrreq : IN STD_LOGIC ; rdreq : IN STD_LOGIC ; clock : IN STD_LOGIC ; aclr : IN STD_LOGIC ; q : OUT STD_LOGIC_VECTOR (7 DOWNTO 0); full : OUT STD_LOGIC ); END fifo2; ARCHITECTURE SYN OF fifo2 IS SIGNAL sub_wire0 : STD_LOGIC_VECTOR (7 DOWNTO 0); SIGNAL sub_wire1 : STD_LOGIC ; COMPONENT lpm_fifo GENERIC (lpm_width : NATURAL; lpm_numwords : NATURAL; lpm_widthu : NATURAL; lpm_showahead : STRING; lpm_hint : STRING); * PORT (rdreq : IN STD_LOGIC ; aclr : IN STD_LOGIC ; clock : IN STD_LOGIC ; q