数字电路设计课件第六讲状态机设计.ppt

状态机设计 状态机设计 LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.all; USE ieee.std_logic_arith.all; ENTITY state_m2 IS PORT(clk, reset, nw : in std_logic; sel: out std_logic_vector(1 downto 0); nxt, first: out std_logic); END state_m2; ARCHITECTURE logic OF state_m2 IS TYPE state_type IS (idle, tap1, tap2, tap3, tap4); SIGNAL filter : state_type; BEGIN Change: PROCESS (reset, clk) 状态机设计 BEGIN IF reset = 1 THEN filter = idle; ELSIF clkevent and clk = 1 THEN CASE filter IS WHEN idle = IF nw = 1 THEN filter = tap1;END IF; WHEN tap1 =filter = tap2; WHEN tap2 =filter =