集成CMOS锁相环设计_.docVIP

重庆大学本科学生毕业设计（论文） 集成CMOS锁相环设计 + 专 业：电子科学与技术 重庆大学光电工程学院 二O一一年六月 Graduation Design(Thesis) of Chongqing University Design of integrated CMOS phase-locked loop College of Optoeletronic Engineering Chongqing University June 2011  摘 要 锁相环的概念自从19世纪30年代提出以来便很快在电子和通信领域中获得了广泛的应用，锁相环路基本上是每一个电路系统都要用到的，因为一个高精度的时钟信号对一个系统的整体性能的影响不言而喻。在所有锁相环结构中，作为数模混合锁相环的典型代表的电荷泵锁相环因其具有锁定相差小、低功耗、低抖动和捕获范围大等明显优势而成为了当前设计的主要形式。 文章首先研究了锁相环的基本理论，再对锁相环的各部分结构与模型进行了的讨论与研究。本文采用了从上至下的方法对电荷泵锁相环进行了设计，首先从系统层面研究了它的模型和指标，然后再进行晶体管级电路图的设计与仿真。本文所设计的电荷泵锁相环工作在5V电源电压，锁定频率达100MHz。 对电路结构进行分析之后选择了普通边沿触发形式的鉴频鉴相器，可消除时钟馈通和电荷共享的电荷泵以及能滤除高频电压噪声的低通滤波器，差分放大器是VCO设计中最重要的模块，本文采用了五级差分环形振荡器，这将极大提高对来自电源和衬底噪声干扰的抑制能力，从而得到增益线性度更高的输出信号波形。 本文的设计采用 Cadence Virtuoso工具，在CSMC 2P3M工艺下进行了仿真。经过仿真，电路各部分及整体的性能均可以达到设计指标。 关键词：锁相环；电荷泵；低通滤波器；差分环形振荡器 Abstract The phase-locked loop ,widely used in electronics and communications since the concept of it was proposed in 1830s ,which is now almost applied in every circuit system because how important is a high precision clock signal for the whole system is self-evident. As a typical representative of the digital and analog mixed circuits with the obvious advantages of small phase-locked error，low power dissipation ,low jitter, and wide capture limits，the charge-pump phase-locked loop is now the Main design form of PLL among all the structures. This thesis begins from the basic theory research of PLL and has brief studied every part’s structure and model. We have first studied the CPPLL(Charge-Pump Phase-Locked Loop) system level and then we have researched the CMOS transistor level. The CPPLL designed in this text works at 5V and is locked at 100MHz. The thesis chooses the con-PFD(Common mode Phase-Locked Loop), a charge pump without clock feed through effective and charge share and a low pass filter eliminates high frequency voltage noise after the analysis of the circuit structure. VCO is the most important module in the design of CPPLL and in this thesis the VCO is a five stage differential ri