基于北斗 GPS秒脉冲的高稳时钟源设计精选.pdfVIP

Computer Science and Application 计算机科学与应用, 2017, 7(1), 1-7 Published Online January 2017 in Hans. /journal/csa /10.12677/csa.2017.71001 Design of High Stable Clock Source Based on Beidou/GPS Second Pulse Jianguo Yang, Ruifeng Fu, Xufang Huang Computer and Electronic Information College, Guangxi University, Nanning Guangxi th th th Received: Dec. 27 , 2016; accepted: Jan. 14 , 2017; published: Jan. 17 , 2017 Abstract Based on the UM220IIIN double system receiver and FPGA, a clock source of the Beidou or GPS second pulse high stability is designed in this paper. Two UM220IIIN receive the second pulse of Beidou satellite and GPS, inputting to the cyclone IV chip of FPGA, and then it is first to judge the validity of the second pulse signal of Beidou and GPS. If the two second pulses are valid, they were carried out by the high frequency count in 10 seconds, and counting is based on the use of FPGA internal own high-frequency clock; if only one way is valid, only the effective second pulse is counted. Then calculating the mean and variance of the count in 10 seconds, the best second pulse or the effective branch of the second pulse is output by comparing the variance of the second pulse. If the second pulse of Beidou satellite and GPS are invalid and the use of FPGA internal clock and historical data predict next output cycle of the second pulse, the system can continue to output high precision of the second pulse as a clock source. Keywords Timing Source, Beidou Satellite, GPS, FPGA 基于北斗/GPS秒脉冲的高稳时钟源设计 杨建国，傅瑞峰，黄旭方 广西大学，计算机与电子信息学院，广西 南宁 收稿日期：2016年12月27 日；录用日期：2017年1月14 日；发布日期：2017年1月17 日 摘 要 基于UM220IIIN双系统接收机和FPGA，设计一种北斗/G