基于嵌入式LINUX的VoIP终端设计 英文翻译.docVIP

本 科 毕 业 论 文 基于嵌入式LINUX的VoIP终端设计 文献翻 译 学院名称：计算机科学与通信工程学院 专业班级： 通信 学生姓名： 指导教师姓名： 指导教师职称： 教 授 2009 年 4 月 Chapter 5. Performance Guidelines 5.1 Instruction Performance To process an instruction for a warp of threads, a multiprocessor must: ‰ Read the instruction operands for each thread of the warp, ‰ Execute the instruction, ‰ Write the result for each thread of the warp. Therefore, the effective instruction throughput depends on the nominal instruction throughput as well as the memory latency and bandwidth. It is maximized by: ‰ Minimizing the use of instructions with low throughput (see Section 5.1.1), ‰ Maximizing the use of the available memory bandwidth for each category of memory (see Section 5.1.2), ‰ Allowing the thread scheduler to overlap memory transactions with mathematical computations as much as possible, which requires that: The program executed by the threads is of high arithmetic intensity, that is, has a high number of arithmetic operations per memory operation; There are many threads that can be run concurrently as detailed in Section 5.2. 5.1.1 Instruction Throughput 5.1.1.1 Arithmetic Instructions To issue one instruction for a warp, a multiprocessor takes: ‰ 4 clock cycles for floating-point add, floating-point multiply, floating-point multiply-add, integer add, bitwise operations, compare, min, max, type conversion instruction; ‰ 16 clock cycles for reciprocal, reciprocal square root, __log(x) (see Table B-2). 32-bit integer multiplication takes 16 clock cycles, but __mul24 and __umul24 (see Appendix B) provide signed and unsigned 24-bit integer multiplication in 4 clock cycles. On future architectures however, __[u]mul24 will be slower than 32- bit integer multiplication, so we recommend to provide two kernels, one using__[u]mul24 and the other using generic 32-bit integer multiplication, to be called appropriately by the applicatio