Layout教程--台湾黄弘一.pdf

Chapter 1 CMOS Processing Flow - 0.25um 1P5M - 0.18um 1P6M - 0.15um 1P7M - 0.13um 1P8M - 0.09um - Copper Interconnection - Mixed-Signal / RF - CMOS Processing - Processing Integration 1 Hong-Yi Huang黃弘一 TSMC 0.25um 1P5M 2 Hong-Yi Huang黃弘一 TSMC 0.18um 1P6M 3 Hong-Yi Huang黃弘一 TSMC 0.15um 1P7M 4 Hong-Yi Huang黃弘一 TSMC 0.13um 1P8M 5 Hong-Yi Huang黃弘一 0.09um TSMC unveiled its full 90-nanometer technology under the brand name Nexsys and, at the same time announced that 90-nanometer risk production would start in September of 2002. Volume production of the Nexsys 90-nm process will be manufactured on 300mm wafers. Nexsys technology satisfies the power, performance and integration requirements of a broad spectrum of applications and includes high- performance, low-power, mixed-signal/RF, and embedded memory options. TSMC established the Nexsys brand for its next-generation SOC process technology platform. The companys 90-nm technology is the first TSMC process to adopt this brand. Nexsys offers a unique triple gate oxide option that facilitates three different oxide thicknesses on a single chip. The triple gate oxide feature removes design restrictions caused by various core/IO combination requirements and should lead to more innovative SOC designs. With 70-75% linear shrinkage and a two-times performance improvement,