synopsys学习资料-cy7c1371c.pdf

CY7C1371C CY7C1373C 18-Mbit (512K x 36/1M x 18) Flow-Through SRAM with NoBL™ Architecture Features Functional Description[1] • No Bus Latency™ (NoBL™) architecture eliminates The CY7C1371C/CY7C1373C is a 3.3V, 512K x 36/ 1M x 18 dead cycles between write and read cycles Synchronous Flow-through Burst SRAM designed specifically • Can support up to 133-MHz bus operations with zero to support unlimited true back-to-back Read/Write operations without the insertion of wait states. The CY7C1371C/ wait states CY7C1373C is equipped with the advanced No Bus Latency™ — Data is transferred on every clock (NoBL™) logic required to enable consecutive Read/Write • Pin compatible and functionally equivalent to ZBT™ operations with data being transferred on every clock cycle. devices This feature dramatically improves the throughput of data through the SRAM, especially in systems that require frequent • Internally self-timed output buffer control to eliminate Write-Read transitions. the need to use OE All synchronous inputs pass throug