什么是FPGA现场可编程门阵列FPGA是由通过可编程互连连接的可配置.PDF

FPGA (FPGA) (CLB) (ASIC) FPGA (OTP) FPGA SRAM 1 FPGA IOB FPGA I/O FPGA I/O bank () bank I/O FPGA I/O bank I/O CLB FPGA CLB 4 6 RAM CLB DCM FPGA Xilinx FPGA FPGA FPGA FPGA RAM DSP ASIC FPGA (CLB) CLB FPGA CLB 4 6 RAM CLB CLB I/O CLB SelectIO (IOB) FPGA I/O FPGA I/O bank () bank I/O FPGA I/O bank I/O FPGA RAM Xilinx FPGA 10 Mbits ( 36 Kbits) FPGA Xilinx FPGA Xilinx FPGA FPGA FPGA Xilinx FPGA IP SDR FPGA IP IP // (NAS)(SAN) RF WCDMA HSDPAWiMAX /MAC DSP Xilinx XtremeDSP™ DSP Xilinx ASIC FPGA ASIC FPGA : FPGA ASIC FPGA ASIC - - NRE - ASIC - - - - - FPGA / / FPGA 500 MHz FPGA DSP FPGA ASIC FPGA FPGA / Xilinx CPLD ? CPLD // , CPLD This performance boost came at the cost of very high current requirements. XilinxCoolRunner™-II CPLD CPLD CoolRunner-II CPLD CPLD X RealDigital X X CoolRunner-II RealDigital (PDF) CPLD? CPLD - ASIC - CPLD - TTL ASSP - CPLD Xilinx CPLD? Xilinx CPLD - I/O - ISE® WebPACK™ Xilinx CPLD - Xilinx CPLD CPLD CPLD : 4 1 CPLD CPLD I/O ISE® WebPACK™ Xilinx CPLD I/O Xilinx CPLD CPLD ISE WebPACK Xilinx CPLD I/O Xilinx CPLD QFP I/O BGA Xilinx CPLD CoolRunner™ Series Xilinx CoolRunner CPLD CPLD I/O banking XC9500 5.0V (XC9500 ) 3.3V (XC9500XL ) CPLD 2 CPLD FGPA CPLD