[2018年最新整理]AltiumDesigner基于FPGA系统设计功能培训.pptVIP

* 虚拟仪器 IO模块 数字IO模块是一款用于监测和使能电路信号的通用工具，可以支持8位或16位信号的输入/输出。利用面板上的模拟LED显示，就可以直观的获取信号线上电平的状态。 * 结束 谢谢大家！！！ support@ * Altium2005 Next Step Altium为设计电子产品和设备的公司提供协同化、集成化、先进的、易用的 电子产品开发方案。区别于Mentor、Zuken、Candence，Altium更关注于提供 主流设计解决方案。因此，我们的解决方案总能以比较低的花费获取我们最好 的产品技术和性能。 * Appendix B – Overview of JTAG Boundary-Scan standard developed proposed by Joint Test Action Group (JTAG) IEEE1149.1 - 2001, Standard Test Access Port and Boundary-Scan Architecture Defines: Circuitry to implement in the IC Standard interface through which instructions test data are communicated Set of test features, including a boundary-scan register to assist with testing A language to allow rigorous description of testability features Standard available from IEEE at www.IEEE.org * Appendix C – Overview of Nexus protocol IEEE-ISTO 5001 – 1999, Standard for a Global Embedded Processor Debug Interface Leverages IEEE 1149.1 standard interface (JTAG) Defines: Register functions Pin functions Transfer protocols Standard downloadable at * * One important area of the design process is integrating the FPGA design with the design of the final PCB. While Nexar doesn’t support board design directly, it uses the same platform the same design capture environment as Altium’s Protel board-level design system. Because of this, we have released a new version of Protel – Protel 2004 - to make the integration of the FPGA system design the final board design easier. As Nexar Protel share capture environments, Protel 2004 will work natively with Nexar project files. This allows us to implement features such as automatic optimization of the pin out of the FPGA in Protel for board layout routing, automatic back annotation of pin changes back to both the board-level schematic the FPGA project. * 下面来看一下在FPGA设计过程中的系统控制部分， 首先以图形化的方式来完成整个设计流程 系统自动调用FPGA厂商提供的工具进行布局布线 设计环境中的集中过程控制和监测功能使得信息能够得到及时反馈从而实现交互式设计与调试 Altium称这种交互式设计方法为“LiveDesign” *