[工程科技]A96-ChannelFPGA-basedTime-to-DigitalConverter.pdfVIP

EFI-04-42 A 96-Channel FPGA-based Time-to-Digital Converter Mircea Bogdan, Henry Frisch, Mary Heintz, Alexander Paramonov, and Harold Sanders Enrico Fermi Institute, University of Chicago 5 0 0 Steve Chappa, Robert DeMaat, Rod Klein, Ting Miao, and Peter Wilson 2 Fermilab National Accelerator Laboratory b e F Thomas J. Phillips 1 1 Duke University ] t Abstract e d - We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with s n i. the Central Outer Tracker (COT) [1] in the CDF Experiment [2] at the Fermilab Tevatron. The s c COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The i s y TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed h p in firmware in two Altera Stratix FPGA’s. The special capabilities of this device are the availability [ 1 of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC v 2 system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a 6 0 minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The 2 0 time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling 5 0 a circular memory; the memory addresses of logical transitions (edges) in the input data are then / s c translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth i s y of 5.5 µs allow deadtime-less operation in the first