EDAVHDL编程.docVIP

计数器  = 1 \* GB3 ① ENTITY CNT4 IS PORT ( CLK , EN: IN BIT; q : BUFFER INTEGER RANGE 15 downto 0); END; ARCHITECTURE bhv of cnt4 IS begin process (clk) begin if clk=1 then if en=1 then q=q+1; elsif EN=0 then q=q-1; end if; end if; end process; end bhv;  = 2 \* GB3 ② library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity scan is port ( clk : in std_logic; show:out std_logic_vector(6 downto 0) ); end; architecture one of scan is signal cnt: std_logic_vector(2 downto 0); signal k: std_logic_vector(7 downto 0