VHDL语言教学幻灯片讲义.pptVIP

第四章 VHDL语言; I 数据选择器VHDL描述;ENTITY mux21 IS PORT(a,b:IN BIT; s:IN BIT; y:OUT BIT); END ENTITY mux21; ARCHITECTURE one OF mux21 IS BEGIN y=(a AND (NOT s)) OR (b AND s); END ARCHITECTURE one; ;一个可综合的vhdl描述的基本逻辑结构中：实体和结构体是必需的;[例4-2];…… ARCHITECTURE one OF mux21 IS BEGIN y = a WHEN s=0 ELSE b ; END ARCHITECTURE one;;ENTITY mux21 IS PORT(a,b,s:IN BIT; y: OUT BIT); END ENTITY mux21; ARCHITECTURE one OF mux21 IS BEGIN PROCESS(a,b,s) BEGIN IF s=‘0’ THEN y= a; ELSE y=b; END IF; END PROCESS;