verilog设计一四位计数器.doc

FPGA与硬件描述语言实验报告 学院： 信息技术学院 班级： 专业： 电子信息科学与技术 姓名： 日期： 学号： 实验目的 熟悉行为级语法； 熟悉有限状态机 2.1实验内容 设计一四位计数器，进行仿真，并检测输出结果； 提示：在时钟上升沿，如果复位信号有效，则复位为0,如果复位信号无效，则计数器需要加一。 output z; reg z; input clock, clear; input x; parameter s0 = 3d0, s1 = 3d1, s2 = 3d2, s3 = 3d3, s5 = 3d5, s4 = 3d4; reg [2:0] state; reg [2:0] next_state; always @(posedge clock) if(clear) state = s0; else state = next_state; always @(state) begin case(state) s0: show = 0; s1: show = 0; s2: show = 0; s3: show = 0; s4: show = 0; s5: show = 1; endcase end always @(x or state) begin case(state) s0: if(x == 0) next_state = s0; else next_state = s1; s1: if(x == 0) next_state = s2; else next_state = s1; s2: if(x == 0) next_state = s3; else next_state = s1; s3: if(x == 0) next_state = s0; else next_state = s4; s4: if(x == 0) next_state = s5; else next_state = s1; s5: if(x == 0) next_state = s0; else next_state = s1; endcase end endmodule 3.2测试模块代码 module stimulus_mv; wire z; reg x; reg clock, clear; mianMVP(z, x, clock, clear); initial begin clock = 0; forever #5 clock = ~clock; end initial begin clear = 1; repeat(2)@(negedge clock); clear = 0; end initial begin #30 x = 1; #10 x = 0; #10 x = 0; #10 x = 1; #10 x = 0; end endmodule 3.3仿真结果： 输出： 四位计数器 3.1功能块代码 module counter(out, clock, clear); output out; input clock, clear; reg [3:0] out; always @(posedge clock or negedge clear) begin if(clear) out = 4d0; else out = out + 1; end endmodule 3.2测试模块代码 module counter_stimulus; reg clock, clear; wire