[工学]Verilog的用途.ppt

晚到达的是数据信号 晚到达的是控制信号 如果晚到达信号作为if语句条件分支的条件，也应使这个信号离输出最近。在下面的例子中，CTRL_is _late是晚到达的控制信号 module single_if_late(A, C, CTRL_is_late, Z); input [6:1] A; input [5:1] C; input CTRL_is_late; output Z; reg Z; always @(C or A or CTRL_is_late) if (C[1] == 1’b1) Z = A[1]; else if (C[2] == 1’b0) Z = A[2]; else if (C[3] == 1’b1) Z = A[3]; else if (C[4] == 1’b1 CTRL_is_late == 1’b0) // late arriving signal in if condition Z = A[4]; else if (C[5] == 1’b0) Z = A[5]; else Z = A[6]; endmodule 晚到达的是控制信号 module single_if_late(A, C, CTRL_is_late, Z); input [6:1] A; input [5:1] C; input CTRL_is_late; output Z; reg Z; always @(C or A or CTRL_is_late) // late arriving signal in if condition if (C[4] == 1’b1 CTRL_is_late == 1’b0) Z = A[4]; else if (C[1] == 1’b1) Z = A[1]; else if (C[2] == 1’b0) Z = A[2]; else if (C[3] == 1’b1) Z = A[3]; else if (C[5] == 1’b0) Z = A[5]; else Z = A[6]; endmodule if-case嵌套语句 module case_in_if_01(A, DATA_is_late_arriving, C, sel, Z); input [8:1] A; input DATA_is_late_arriving; input [2:0] sel; input [5:1] C; output Z; reg Z; always @ (sel or C or A or DATA_is_late_arriving) if (C[1]) Z = A[5]; else if (C[2] = = 1’b0) Z = A[4]; else if (C[3]) Z = A[1]; else if (C[4]) case (sel) 3’b010: Z = A[8]; 3’b011: Z = DATA_is_late_arriving; 3’b101: Z = A[7]; 3’b110: Z = A[6]; default: Z = A[2]; endcase else if (C[5] = = 1’b0) Z = A[2]; else Z = A[3]; endmodule if-case嵌套语句 Case语句 if语句 if-case嵌套语句—修改后 always @(sel or C or A or DATA_is_late_