[工学]EDA技术概述.ppt

module dff_pos(data，Clk，q); //define a module dff_pos for D flip- flop input data，clk; output q; reg q; always@(posedge clk) q=data; endmodule //everything is OK for Verilog HDL description --a library name must be defined at the beginning of description Library ieee; Use .std_logic_1164.all; Entity dff_pos is port(data.clk:in std_logic; q:out std_logic); End dff_pos; Architecture rt1 of dff_pos is Begin infer:process(clk)begin If(clk’event and clk=‘1’)then q=data; end if End process infer;