VHDL双语教学第3章教材教学课件.pptVIP

VHDL;Agenda;Basic Language Framework;Agenda;Entity;Entity Definition;Entity Examples (ROM);Entity Examples (Adder);Entity Examples (n-input AND);Entity Example (Empty Entity);Port Examples (ROM);Port Examples (Adder);Port Examples (n-input AND);Port Definition;Each Parts of Port;Type of “Dir”;Signal Direction;Dir Example;Use of Dir;Type;Typical Port Type;Bit;Bit_vector;Std_logic;Resolution Function Of Std_logic;Std_logic_vector;Agenda;Entity Definition (Generics);An AND Gate With Unknown Inputs;Generic Definition;Generic Example (1);Use of the Generic (ANDN.vhd);Use of the Generic (My_package.