硬件结构设计.docxVIP

摘要：本次实验的功能是进行两个4位数的加法运算，并进行结果输出。在本次实验中，我们用到data_bus作为总线进行传输，reg_74373作为寄存器进行数据的存储，alu_74181进行加法运算。romc作为译码器进行初始状态的设定。通过这个加法器的设计，能够对硬件结构设计有了更好的了解，同时也加深了对计算机组成原理课程的理解。硬件结构设计原理：1.把模块romc改为九位输出oen,we1,we2,gwe1,oen_n1,gwe2,oen_n2,gwe3,oen_n3；2.把模块reg_74244改为四位输入Din(3 0)和四位输出Qout(3 0)；3.把模块data_bus改为四位输入data_in1(3 0),Data_in2(3 0),四位输出data_out1(3 0),data_out2(3 0),data_out3(3 0);4.把模块reg_74373改为四位输入Din(3 0)和四位输出Qout(3 0)；5.把模块alu_74181改为四位输入A(3 0),B(3 0),S(3 0),和四位输出F(3 0)6.由romc向reg_74244中分别输入两个四位二进制的数，通过九位romc微程序控制器，在进入data_bus后，两个数分别被写入两个reg_74373中，再进入alu_74181进行加法运算，将运算结果输入data_bus，再由另外一个reg_74373读出。原理图：管脚图：###------------CLOCK-----------NET clk LOC = L15;###-------------Atlys led output-------------------#NET atlys_led[0] LOC = U18; #Atlys LD0#NET atlys_led[1] LOC = M14; #Atlys LD1#NET atlys_led[2] LOC = N14; #Atlys LD2#NET atlys_led[3] LOC = L14; #Atlys LD3#NET atlys_led[4] LOC = M13; #Atlys LD4#NET atlys_led[5] LOC = D4; #Atlys LD5#NET atlys_led[6] LOC = P16; #Atlys LD6#NET atlys_led[7] LOC = N12; #Atlys LD7###-----------Atlys Switch input-------------------#NET atlys_sw[0] LOC = A10; # Atlys sw0#NET atlys_sw[1] LOC = D14; # Atlys sw1#NET atlys_sw[2] LOC = C14; # Atlys sw2#NET atlys_sw[3] LOC = P15; # Atlys sw3#NET atlys_sw[4] LOC = P12; # Atlys sw4#NET atlys_sw[5] LOC = R5; # Atlys sw5#NET atlys_sw[6] LOC = T5; # Atlys sw6#NET atlys_sw[7] LOC = E4; # Atlys sw7###------------EES261 switch input----------NET din[0] LOC = U11; #SW20NET din[1] LOC = R10; #SW19NET din[2] LOC = U10; #SW18NET din[3] LOC = R8; #SW17NET S[0] LOC = M8; #SW16NET S[1] LOC = U8; #SW15NET S[2] LOC = U7; #SW14NET S[3] LOC = N7; #SW13#NET C_n LOC = T6; #SW12#NET C_n_Plus LOC = R7; #SW11#NET XLXN_9 LOC = N6; #SW10#NET swt[8] LOC = U5; #SW9#NET swt[7] LOC = V5; #SW8#NET swt[6] LOC = P7; #SW7#NET swt[5] LOC = T7; #SW6#NET swt[4] LOC = V6; #SW5NET s0 LOC = P8; #SW4NET s1 LOC = V7; #SW3NET s2 LOC