EDA技术--数字电子钟的设计.docVIP

电子信息工程专业项目化课程 四 、VHDL语言编程设计 4.1、 60进制设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jinzhi60 is port (ctp,nreset,clk1s:in std_logic; co:out std_logic; qhh:out std_logic_vector(3 downto 0); qll:out std_logic_vector(3 downto 0)); end jinzhi60; architecture behave of jinzhi60 is signal ql,qh:std_logic_vector(3 downto 0); begin co=1 when (qh=0101 and ql=1001 and ctp=1) else0; process(clk1s,nreset,ctp) begin if(nreset=0)then qh=0000; ql=0000; elsif(clk1s event and clk1s=1)then if(ctp=1)then if (qh=0101 and ql=1001)then qh=0000; ql=0000; elsif(ql9)then ql=ql+1; else ql=0000; qh=qh+1; end if; end if; end if; qhh=qh; qll=ql; end process; end behave; 4.2、24进制设计 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity jinzhi24 is port (ctp,nreset,clk1s:in std_logic; co:out std_logic; qhh:out std_logic_vector(3 downto 0); qll:out std_logic_vector(3 downto 0)); end jinzhi24; architecture behave of jinzhi24 is signal ql,qh:std_logic_vector(3 downto 0); begin co=1 when (qh=0101 and ql=1001 and ctp=1) else0; process(clk1s,nreset,ctp) begin if(nreset=0)then qh=0000; ql=0000; elsif(clk1s event and clk1s=1)then if(ctp=1)then if (qh=0101 and ql=1001)then qh=0000; ql=0000; elsif(ql9)then ql=ql+1; else ql=0000; qh=qh+1; end if; end if; end if; qhh=qh; qll=ql; end process; end behave; 4.3、动态扫描 library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity datm is port(clk:in bit; a,b,c,d,e,f:in std_logic_vector(3 downto 0); w:out std_logic_vector(2 downto 0); q:out std_logic_vector(6 downto 0)); end datm; architecture wei of datm is signal qq:std_logic_vector(3 downto 0); signal cntt:std_logic_vector(2 downto 0); begin process(clk) variable cnt:std_logic_vector(2 downto 0); begin if clkevent and clk=1 then if cnt5 then cnt:=cnt+1; else cnt:=000; end if; cntt =cnt; case cnt is when 000=qq=a; when 001=