[信息与通信]CMOS乘法器版图设计与仿真——第1章-第4章.docVIP

[信息与通信]CMOS乘法器版图设计与仿真——第1章-第4章.doc

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[信息与通信]CMOS乘法器版图设计与仿真——第1章-第4章

摘 要 先进的系统为实现高速算术运算都包含有乘法器通常乘法器处于关键延时路径上,因此乘法器的速度对整个系统性能有重要影响。通常乘法器速度取决于算法及结构按结构可分为串行乘法器和并行乘法器,串行乘法器面积和功耗最小,但是运算速度也最慢,因此高速数字应用系统通常会采用并行乘法器。因此高速数字应用系统通常会采用并行乘法器。并行乘法器 关键词: 数字乘法器;并行乘法器;串行乘法器;加法器阵列 Abstract With the fast development of integrate circuit technology, the use of powerful EDA tools in the digital design is needed while the scale and the complex of design has increased incessant, also the design cycle is shorted. Especially the micron-electronics with deep-inferior micron, the integration degree of the single slice can be reached to millions transistor, the change of technology has a great effect with the chips, even with the success or fail of system design. This paper is mainly about how to use the cadence EDA tools which developed with the company of cadence to design a CMOS Digital Multiplier. In this paper is mainly introduced the main principle of the digital array multiplier and discussed the advantage of each other. Then 4X4 bit serial multiplier and 4X4 bit parallel multiplier have been designed, we discussed the delay and the area of both multiplier. With the stimulate of the layout of both 4X4 bit multipliers, inproved that the 4X4 bit parallel multiplier is much speeder than 4X4 bit serial multiplier, so the parallel multiplier is always used in the high speed digital application system. Put forward the design of 8X8 bit parallel multiplier which based on the administrative levels. Designed the sign bit extension and finished the schematic, layout and stimulation with layout of 8X8 bit parallel multiplier with sign bit extension. The stimulation wave is shown with delay parameter. Put forward the design of optimized 8X8 bit parallel multiplier, optimized the old design of 8X8 bit parallel multiplier with sign bit extension and finished its schematic, layout and stimulation of layout. And have a comperation of the speed and used area between optimized multiplier with old design. With the result parameter of stimulation of layout, improved t

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