第6章 指令流水线.ppt

Notice that although the branch instruction is fetched during Cycle 4, its target address is NOT written into the Program Counter until the end of clock Cycle 7. Consequently, the branch target instruction is not fetched until clock Cycle 8. In other words, there is a 3-instruction delay between the branch instruction is issued and the branch effect is felt in the program. This is referred to as Branch Hazard in the text book. And as we will show in the next lecture, by clever design techniques, we can reduce the delay to ONE instruction. That is if the branch instruction in Location 12 is issued in Cycle 4, we will only execute one more sequential instruction (Location 16) before the branch target is executed. +2 = 71 min. (Y:51) Similarly, although the load instruction is fetched during cycle 1, the data is not written into the register file until the end of Cycle 5. Consequently, the earliest time we can read this value from the register file is in Cycle 6. In other words, there is a 3-instruction delay between the load instruction and the instruction that can use the result of the load. This is referred to as Data Hazard in the text book. We will show in the next lecture that by clever design techniques, we can reduce this delay to ONE instruction. That is if the load instruction is issued in Cycle 1, the instruction comes right next to it (Plus 1) cannot use the result of this load but the next-next instruction (Plus 2) can. +2 = 73 min. (Y:53) The same instruction means the same one as the first instruction add r1, r2, r3 . So the remaining instructions are not affected. Finally, let’s take a look at the end of Cycle 7 where the Branch instruction has just completed its Mem stage. I have assumed the registers we compared in the last cycle are indeed equal so ALU output Zero was asserted and captured in the Ex/Mem register. With Zero asserted and the control signal Branch set to 1, the branch target address we calculated in Cycle 6 and saved in the Ex/M