M48Z08.100PC1;M48Z18.100PC1;中文规格书,Datasheet资料.pdfVIP

M48Z08 M48Z18 ® 5 V, 64 Kbit (8 Kb x 8) ZEROPOWER SRAM Features ■ Integrated, ultra low power SRAM and power- fail control circuit ■ Unlimited WRITE cycles ■ READ cycle time equals WRITE cycle time 28 1 ■ Automatic power-fail chip deselect and WRITE protection ■ WRITE protect voltages PCDIP28 (VPFD = power-fail deselect voltage): Battery CAPHAT™ – M48Z08: VCC = 4.75 to 5.5 V; 4.5 V ≤ VPFD ≤ 4.75 V – M48Z18: VCC = 4.5 to 5.5 V; 4.2 V ≤ VPFD ≤ 4.5 V ■ Self-contained battery in the CAPHAT™ DIP package ■ Pin and function compatible with JEDEC standard 8 K x 8 SRAMs ■ RoHS compliant – Lead-free second level interconnect June 2011 Doc ID 2424 Rev 8 1/20 1 / Contents M48Z08, M48Z18 Contents 1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .