07 Input Output - UW Faculty Web Server07输入输出-威斯康星大学教师的Web服务器.pptVIP

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07 Input Output - UW Faculty Web Server07输入输出-威斯康星大学教师的Web服务器.ppt

07 Input Output - UW Faculty Web Server07输入输出-威斯康星大学教师的Web服务器.ppt

Chapter 7 Input/Output Input/Output Problems Wide variety of peripherals Delivering different amounts of data At different speeds In different formats All slower than CPU and RAM Need I/O modules Generic Model of I/O Module I/O Module Function Support single or multiple devices Hide or reveal device properties Provides: Control Timing CPU Communication Device Communication Data Buffering Error Detection I/O Module Diagram Input Output Techniques Programmed Interrupt driven Direct Memory Access (DMA) Programmed I/O CPU has direct control over I/O Sensing status Read/write commands Transferring data CPU waits for I/O module to complete operation Usually not a good use of CPU time Programmed I/O - detail CPU requests I/O operation I/O module performs operation I/O module sets status bits CPU checks status bits periodically CPU may wait or come back later Interrupt driven I/O - CPU Viewpoint Issue I/O command Do other work - Check for interrupt at end of each instruction cycle When interrupt request is granted:- Save context (registers) Process interrupt Execute “service routine” Continue other work Interrupt Driven I/O – Device Perspective CPU issues I/O command (enable interrupt) I/O module gets data from peripheral while CPU does other work I/O module interrupts CPU (Interrupt request) Device serviced by CPU DMA Function DMA controller(s) takes over from CPU for I/O Additional Module(s) attached to bus Typical DMA Module Diagram DMA Operation CPU tells DMA controller:- Read/Write Device address Starting address of memory block for data Amount of data to be transferred CPU carries on with other work DMA controller deals with transfer DMA controller sends interrupt when finished DMA Transfer Cycle Stealing DMA controller takes over bus for a cycle Transfer of one word of data Not an interrupt CPU does not switch context CPU suspended just before it accesses bus i.e. before an operand or data fetch or a data write Slows down CPU but not as much as CPU doin

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