ch5_逻辑综合.ppt

第5章 逻辑综合及Synopsys Design Compiler使用;概述;综合示意图;综合过程中时序与面积的关系;Design Compiler ( DC ) 简介;DC综合的基本流程;DC综合的基本流程;DC-T 综合流程;Design Compiler 启动界面;Unit1;High-Level Synthesis Flow;High-Level Synthesis Flow;读入设计(Loading Designs);启动DC and 读入 a Flat RTL ;启动DC and 读入 a Flat RTL ;compile需要指定target_library;工艺库的内部描述;设置Target Library ;在DC中许多命令都会首先‘auto-link’if the design has not been linked yet. Linking means that DC tries to locate(定位) the source of, or ‘resolve’(解析) any instances(例化的实体) in the Design. Instances can be gates or sub-blocks(层次化的模块、软核、硬核、DesignWare IP) DC uses the link_library variable to try to resolve the instances. 默认情况下link_library的设置： ;设置link_library;设置好link_library 再执行“link”;Using the search_path Variable;Shortening File name using search_path;DC Startup File;目标库和初始环境的设置;需要指定的库：;.synopsys_dc.setup文件;One Startup File Name – Three File Locations;Default .../admin/setup/.synopsys_dc.setup ;设置工作目录下的.synopsys_dc.setup;Library Setup Exercise;综合脚本实例（.synopsys_dc.setup）;层次化的 RTL Designs;读入层次化的 RTL Designs;Good Practice;Reading design with analyze elaborate;Analyze elaborate;Resolving IP or Macro Library Cells;Reading .ddc Design Files;Saving the ddc before compile;Saving the ddc after compile;Two modes Available for Interconnect RCs;Loading Physical Data;Two-pass Topographical Synthesis Flow;Physical Data Needed by DC-Topographical;UNIX Structure of a Milkyway Reference Lib;标准单元库 ( a standard cell library);“Layout” vs. “Abstract” Views;Technology File (.tf file);TLUPlus files;Layer Mapping File;Milkyway Design Library;Loading Physical Technology Data 1st Time;Default Floorplan Constraints – 1st Synthesis;The Supported DC-T Physical Constraints;Loading Actual Floorplan - 2nd Synthesis;Typical DC-T Flow: example;Unit2;系统层次的划分与基本概念;设计对象：Verilog 透视 ;设计对象：原理图透视;多对象共用一命名;The “get_*” Command;Some handy all_* Command;Summary: Commands Covered;Unit3;电路的设计目标与约束;设计约束;本节概述;面积约束;Setup Hold Time;Launch Latch Edge;Data Arr