台站硬件相关处理机简介-MITHaystackObservatory.PPT

Chinese Real Time VLBI Correlator Xiang Ying, Xu Zhijun, Zhu Renjie, Zhang Xiuzhong, Shu Fengchun, Zheng Weimin Shanghai Astronomical Observatory China 5th International e-VLBI Workshop 17-20 September 2006 OUTLINE Main Characteristics Architecture of the Correlator Clock Module PBI(Playback Interface) Module FFT MAC(Multiply and Accumulate Card) Module MCC(Master Control Card) Module Some results Future Plan Main Characteristics Architecture of Correlator Clock Board In the FFT MAC MCC Chassis: Provide 32MHz clock to pbi module (5 stations) Provide 32MHz clock to FFT+MAC module (8 channels) Provide 32MHz clock to MCC Provide 32MHz clock to LTA PBI 1. Input buffer 2. NRZM(Non Return to Zero Mark) decoding（MK IV） 3. Frame Synchronization detection and frame header information extraction 4. CRC checks and Parity check(MK IV） 5. Fanout（1 : 1、1 : 2、1 : 4） 6. Output buffer PBI Data Stream FFT MAC Board Diagram FFT (Fast Fourier Transform) Model Parameter MAC (multiple and accumulate) FFT MAC Board MCC MCC Board Result – TC-1 Satellite Results - SMART-1 DVLBI observation Results (Cont.) Future Plan VSI FITS format Thanks ? * * 5 Stations FX Correlator ( 5 stations, 8 IFs ) Maximum data rate：256Mbps (8 channels) Integration Time：32.768 millisecond – 1 hour (typical 1s) Input data format: MKIV, MKV or others( VSI in plan) data source ：Disk Array, Network Output: via net and disk files ( FITS format in plan) Fringe searcher, Phase Cal PBD CCC+LTA MOXA Card PBI (xc2v3000) FFT MAC (xc4vsx35) MCC (xc4vFX20) 8K X 32bit 15 X 32bit CRC checks Check Strip off parity 15 X 8bit 1:1 1:2 1:4 SYSTEM_CLK ……111111110111111110111111110111111110…… sync pattern Input buffer NRZM decoding Data checks fanout Frame sync、 Frame header Output buffer MK V 数据通道 MK V Data MK IV 数据通道 MK IV data 8K X 32bit 15 X 32bit 15 X 8bit D CLK DATA + WR_CLK ACK FFT_CLK Ready Data Output M A C FFT 16bits Scaled Fixed Point F R I N G E D E L A Y 16bits LTA 7300A Model Input F S